| SIA
Roadmap |
Key
Problems |
AMITEC
MCP |
| High Chip Power @ Low Vdd |
Very High Supply Current |
Off-Chip Power Distribution |
| Small Feature/ Line Size |
Very High Line Resistance |
Off Chip Busses |
| Logic with RAM on Chip |
Process Optimization |
Build high Density RAM with Optimized
IC Process Separate from Logic |
| Large Die Size |
Poor Yield (Defect Density) |
Optimize Die Size for Yield without
Limits on Complexity and Functionality |
| Number of Transistors per I/O Pin |
Access/Personalization for Various
Applications |
Block-Level Access to Resources |
| Many On-Chip Metal Layers |
Complex Process |
Parallel Processing of Substrate and
Chip |